Power Efficient Digital LDO Regulator with Transient Response Boost Technique
Abstract
A digital low-dropout regulator (D-LDO) with reduced transient response time and overshoot/undershoot is proposed. The reduction of response time is achieved by using transient response boost technique. The loop gain is increased at the time of deviations exceeding the limit and the loop gain is returned after the output voltage is settled. On comparing LDO with and without transient response boost technique the settling time is reduced. The regulation is done in time mode with the help of high linear voltage to time convertor (VTC) and time to digital convertor. The time domain analog to digital conversion achieves high resolution at low power and small area. And multibit cyclic TDC for high level current efficiency is used.
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Introduction
Nowadays the battery powered devices are increased and various applications are embedded in a single device as seen in various SoCs. Here the power management unit plays an important role since the power from battery is limited in capacity. The on-chip LDO are gaining more attention as a power management unit. However, most of research works on the lowdropout voltage regulator still focus on the analog control. Compared to the design flow of the analog approach, the digital design flow presents the following difference: designers specify the size of power MOSFET, load requirement, output capacitor value, and its ESR value. In case of analog LDOs driving near threshold and sub-threshold logic circuits a difficulty is imposed in maintaining the low dropout voltage. The time domain ADC can provide higher resolution.
The simple structure of LDO composed of simple convertor consisting binary comparator and shift register. The transient response time is reduced by means of increasing the clock frequency [5] which can be achieved with the help of asynchronous shift register. Multibit ADC provide faster loop operation through direct measurement of voltage difference.TDC based 4-bit ADC with Proportional-Integral-Derivative(PID) controller provide stability compensation and fast transient response is achieved through dynamic clock scaling but it results in high quiescent current. The ADC without PID controller results in higher voltage ripples due to insufficient resolution. Thus power efficient digital linear LDO regulator based on multibit cyclic TDC for high level current efficiency is employed.
Conclusion
In this paper, a digital LDO regulator is proposed operated in time domain using a VTC which has high linearity and large dynamic analog input range. The regulator operates in the time domain to achieve higher resolution. The transient response boost technique is employed to reduce the transient response time without increasing the ripples. The loop gain is increased to maintain stable output voltage by transient response boost technique also improves the current efficiency.