Power Improvement in 64-Bit Full Adder Using Embedded Technologies
Abstract
The adder is most commonly used arithmetic block of CPU (central processing unit) and DSP (digital signal processing), therefore its power and performance optimization is very important. With the scaling of technology to deep submicron, the speed of the circuit increases rapidly. At the same time, the power consumption per chip also increases significantly due to increasing density of the chip. Therefore, in realizing modern VLSI circuits, low power and high speed are the two predominant factors which need to be considered. In this work, there is try to determine the best solution to this problem by improving the performance of adders.
In this work, we improve and compare the power consumption of the three adders. The conventional full adder is built by 28 transistors. So, the transistor count is very high. The average power consumption and delay are very high. In this work, we consider three types of 64-Bit adders and try to improve their performance by varying width and length of substrate. For this purpose, we use tanner tool.
Keywords
Download Options
Introduction
The adder is the most commonly used arithmetic block of the central processing unit and digital signal processing, Therefore its performance and power optimization is of utmost importance. With the technology scaling to deep sub-micron, the speed of the circuit increases rapidly. At the same time, the power consumption per chip also increases significantly due to the increasing density of the chip. Therefore, in realizing modern very large scale integration (VLSI) circuits, low power and high speed are the two predominant factors which need to be considered. Like any other circuit‟s design, the design of high performance and low power adders can be addressed at different level, such as architecture, logic style, layout and the process technology. As a result, there always exists a trade-off between the design parameters such as speed, power, consumption and area.
Arithmetic circuits like adders are one of the basic components in the design of communication circuits. Recently, an overwhelming interest has been seen in the problems of designing digital systems for communication systems and digital signal processing with low power at no performance penalty. Designing low power, high speed arithmetic circuits requires a combination of techniques at four levels; algorithm, architecture, circuit and system levels. The remainder of this paper is organized as follows; section 2 describes the theoretical background. Section 3 describes the circuit designing and implementation of CSL, CPL and DPL adders. While corresponding experimental results and comparison of CSL, CPL and DPL adders are presented in section 4. Conclusion is described in section 5. Finally, future scope is given in section 6.
Conclusion
Focus of this paper was mainly on high performance and low power adder. The adder designed in this work provides the low power requirement. It also presents an area efficient approach to low power, less number of transistors for any design.
64-bit adders were designed in tanner (Evaluation version) tool using 90nm, 130nm and 180nm and analysis of dynamic power dissipation, delay and area was done. Table 1 above shows the power and delay comparison among CSL, CPL & DPL adders. The table 2 above shows comparison between enhanced 64-bit PDP results and base paper 32-bit PDP results.